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By John G. Webster (Editor)

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Threshold Tracking to Control Clock Skew. An important circuit design technique for making clock distribution networks less process sensitive is described by Shoji (125). The technique uses the MOS circuit characteristic that n-channel and p-channel parameters tend not to track each other as a process varies. , an n-channel device will typically cause the p-channel threshold voltage to shift in the opposite direction). Shoji quantitatively describes how the delays of the p-channel and n-channel transistors within the distributed buffers of a clock distribution network should be Race conditions Permissible range TSkewijmin Clock period limitations TSkewijmax CLOCK DISTRIBUTION IN SYNCHRONOUS SYSTEMS P1 P2 P3 Clock' N1 N2 N3 Clock PA PB Clock NA NB Figure 19.

6) must be satisfied. The system-wide clock period is minimized by finding a set of clock skew values that satisfy Eqs. (5) and (6) for each local data path and Eq. (15) for each global data path. These relationships are sufficient conditions to determine the optimal clock skew schedule such that the overall circuit performance is maximized while eliminating any race conditions. The timing characteristics of each local data path are assumed to be known. The minimum clock period is obtained when the problem is formalized as a linear programming problem.

Simulated worst case clock skews of circuits using this technique exhibit skews that are 10% less than that of conventionally designed circuits (125). Interconnect Widening to Minimize Clock Skew Sensitivity. As described in the subsection entitled ‘‘Automated Layout of Clock Distribution Networks,’’ one approach for the automated layout of clock nets is to lengthen specific clock nets to equalize the length of every clock line, thereby keeping the clock skew close to zero. A disadvantage of this approach is that these minimum width lines are very susceptible to variations in the etch rate of the metal lines, as well as to mask misalignment or local spot defects.

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